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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:22:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:22:29 -0700 |
| commit | b780c0a7de3b0f095099461af1434624d2af0c32 (patch) | |
| tree | f1c158b66d1f48110979586264bdb8c211062d02 /backends/aiger | |
| parent | 2c6358ea25d595bf014a564860e3ffde7eddb2cb (diff) | |
| download | yosys-b780c0a7de3b0f095099461af1434624d2af0c32.tar.gz yosys-b780c0a7de3b0f095099461af1434624d2af0c32.tar.bz2 yosys-b780c0a7de3b0f095099461af1434624d2af0c32.zip | |
Allow POs to be PIs in XAIG
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index e93fd35f7..a881b1b88 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -161,12 +161,8 @@ struct XAigerWriter } } - for (auto bit : input_bits) { - if (!bit.wire->port_output) - undriven_bits.erase(bit); - // Erase POs that are also PIs - output_bits.erase(bit); - } + for (auto bit : input_bits) + undriven_bits.erase(bit); for (auto bit : output_bits) if (!bit.wire->port_input) @@ -275,7 +271,8 @@ struct XAigerWriter } } } - if (!abc_box_seen) abc_box_seen = inst_module->attributes.count("\\abc_box_id"); + if (!abc_box_seen) + abc_box_seen = inst_module->attributes.count("\\abc_box_id"); ff_bits.emplace_back(d, q); undriven_bits.erase(q); |