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authorEddie Hung <eddie@fpgeh.com>2020-01-14 13:05:39 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-14 13:05:39 -0800
commitaaafd784a54603af44fe7424c8d39be2443368e5 (patch)
treeaec04b5d96715c0236fa914f9fb8ff361bf4a55f /backends/aiger
parent915e7dde734094e21803f83e37f8827b8ff2fe32 (diff)
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write_xaiger: skip if no arrival times
Diffstat (limited to 'backends/aiger')
-rw-r--r--backends/aiger/xaiger.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index d3415e45d..b424eca2c 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -257,6 +257,9 @@ struct XAigerWriter
arrivals.push_back(atoi(tok.c_str()));
}
+ if (arrivals.empty())
+ continue;
+
if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
GetSize(port_wire), log_signal(it->second), GetSize(arrivals));