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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-03 15:38:18 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-03 15:38:18 -0800 |
| commit | 930f03e8830ed8a8023ff88207b97e757ae8496c (patch) | |
| tree | 55502845f00746f00630a7e2dbddb48e7d33cf7b /backends/aiger | |
| parent | a819656972dd44c479422fa688874926d6239a95 (diff) | |
| download | yosys-930f03e8830ed8a8023ff88207b97e757ae8496c.tar.gz yosys-930f03e8830ed8a8023ff88207b97e757ae8496c.tar.bz2 yosys-930f03e8830ed8a8023ff88207b97e757ae8496c.zip | |
Call -prep_holes before aigmap; fix topo ordering
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index e9b4f07bf..7ef744d04 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -199,7 +199,7 @@ struct XAigerWriter } } - for (auto cell : module->selected_cells()) { + for (auto cell : module->cells()) { if (cell->type == "$_NOT_") { SigBit A = sigmap(cell->getPort("\\A").as_bit()); @@ -613,16 +613,9 @@ struct XAigerWriter if (holes_module) { log_push(); - // Move into a new (temporary) design so that "clean" will only - // operate (and run checks on) this one module - RTLIL::Design *holes_design = new RTLIL::Design; - module->design->modules_.erase(holes_module->name); - holes_design->add(holes_module); - std::stringstream a_buffer; XAigerWriter writer(holes_module); writer.write_aiger(a_buffer, false /*ascii_mode*/); - delete holes_design; f << "a"; std::string buffer_str = a_buffer.str(); |