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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 11:15:25 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-21 11:15:25 -0800 |
| commit | 2f96a0ed32799eba95837d0b64953b889e607c22 (patch) | |
| tree | 0deb54c6320a4bdd74509571ca19e5c607b954bb /backends/aiger | |
| parent | c6fd057eda5dba371ff9c1142019b801bee81111 (diff) | |
| download | yosys-2f96a0ed32799eba95837d0b64953b889e607c22.tar.gz yosys-2f96a0ed32799eba95837d0b64953b889e607c22.tar.bz2 yosys-2f96a0ed32799eba95837d0b64953b889e607c22.zip | |
write_xaiger to use original bit for co, not sigmap()-ed bit
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 56d361fff..b0602dbd8 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -210,9 +210,12 @@ struct XAigerWriter Wire *w = b.wire; if (!w) continue; if (cell->input(c.first)) { - SigBit I = sigmap(b); - if (!w->port_input) - co_bits.insert(I); + if (!w->port_input) { + SigBit I = sigmap(b); + if (I != b) + alias_map[b] = I; + co_bits.insert(b); + } } else if (cell->output(c.first)) { SigBit O = sigmap(b); |