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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 19:36:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 19:36:55 -0700 |
| commit | 2309459605b262040f7bea84e6d935d2838686d5 (patch) | |
| tree | 4d31a758ed0f351a7a53d21174d5686d862ea218 /backends/aiger | |
| parent | 9ec57b46c2f37ca9eafca8e0e919d676c74f99d8 (diff) | |
| download | yosys-2309459605b262040f7bea84e6d935d2838686d5.tar.gz yosys-2309459605b262040f7bea84e6d935d2838686d5.tar.bz2 yosys-2309459605b262040f7bea84e6d935d2838686d5.zip | |
Do not treat $__ABC_FF_ as a user cell
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ce2f6e571..923ba3da8 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -222,15 +222,15 @@ struct XAigerWriter log_assert(!holes_mode); - // FIXME: Should short here, rather than provide $__ABC_FF_ - // to ABC like a user cell - //if (cell->type == "$__ABC_FF_") - //{ - // SigBit D = sigmap(cell->getPort("\\D").as_bit()); - // SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); - // alias_map[Q] = D; - // continue; - //} + if (cell->type == "$__ABC_FF_") + { + SigBit D = sigmap(cell->getPort("\\D").as_bit()); + SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); + unused_bits.erase(D); + undriven_bits.erase(Q); + alias_map[Q] = D; + continue; + } RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr; bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false; |