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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 11:49:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 11:49:57 -0800 |
| commit | 1ccee4b95e1e7a2edf55c989d6acc7d6f63762ba (patch) | |
| tree | 6014022c0a9e010e0bea36eff1bd1919133e10b0 /backends/aiger | |
| parent | 45d9caf3f9771a3f6289b745ff2bb631e6e16f06 (diff) | |
| download | yosys-1ccee4b95e1e7a2edf55c989d6acc7d6f63762ba.tar.gz yosys-1ccee4b95e1e7a2edf55c989d6acc7d6f63762ba.tar.bz2 yosys-1ccee4b95e1e7a2edf55c989d6acc7d6f63762ba.zip | |
write_xaiger: sort holes by offset as well as port_id
Diffstat (limited to 'backends/aiger')
| -rw-r--r-- | backends/aiger/xaiger.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index b6a7dbac2..7ee5058ae 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -474,7 +474,8 @@ struct XAigerWriter if (holes_mode) { struct sort_by_port_id { bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const { - return a.wire->port_id < b.wire->port_id; + return a.wire->port_id < b.wire->port_id || + (a.wire->port_id == b.wire->port_id && a.offset < b.offset); } }; input_bits.sort(sort_by_port_id()); |