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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-06 10:20:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-06 10:20:30 -0800 |
| commit | 91a7a74ac438ba5b030d90fcfafeb1db03757d91 (patch) | |
| tree | 91b62605ba778167dff37b4b2cc55ea13b83e29a /backends/aiger/xaiger.cc | |
| parent | 2335c59e5bdd40c16ced821a27de7df00016963a (diff) | |
| download | yosys-91a7a74ac438ba5b030d90fcfafeb1db03757d91.tar.gz yosys-91a7a74ac438ba5b030d90fcfafeb1db03757d91.tar.bz2 yosys-91a7a74ac438ba5b030d90fcfafeb1db03757d91.zip | |
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 402f41597..7b6b851b3 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -174,11 +174,12 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - bool keep = wire->get_bool_attribute(ID::keep); - if (wire->port_input || keep) + bool scc = wire->attributes.count(ID(abc9_scc)); + if (wire->port_input || scc) input_bits.insert(bit); - if (wire->port_output || keep) { + bool keep = wire->get_bool_attribute(ID::keep); + if (wire->port_output || keep || scc) { if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); |