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| author | Clifford Wolf <clifford@clifford.at> | 2017-03-02 16:39:48 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-03-02 16:39:48 +0100 |
| commit | a6ca28276e3786ba3d756f46d7804a6dcf1e5b11 (patch) | |
| tree | 01ac2fed3cae32514a7d58c220261896e9acdb18 /backends/aiger/aiger.cc | |
| parent | 5b3b5ffc8cb1a3dcc846c5f62ffb5e0cffb9e055 (diff) | |
| download | yosys-a6ca28276e3786ba3d756f46d7804a6dcf1e5b11.tar.gz yosys-a6ca28276e3786ba3d756f46d7804a6dcf1e5b11.tar.bz2 yosys-a6ca28276e3786ba3d756f46d7804a6dcf1e5b11.zip | |
Add write_aiger $anyseq support
Diffstat (limited to 'backends/aiger/aiger.cc')
| -rw-r--r-- | backends/aiger/aiger.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 02871a6fd..5bc268437 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -188,6 +188,13 @@ struct AigerWriter continue; } + if (cell->type == "$anyseq") + { + for (auto bit : sigmap(cell->getPort("\\Y"))) + input_bits.insert(bit); + continue; + } + log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); } |