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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-30 15:35:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-30 15:37:46 +0200 |
| commit | 84f3a796e1232b19674a412b5d011d208d923f5c (patch) | |
| tree | 8a420ad47ea427e05d0775432eb60ced03b7618a /__init__.py | |
| parent | 9268cd16135db87920ee49a54a16dab62fc1f4a8 (diff) | |
| download | yosys-84f3a796e1232b19674a412b5d011d208d923f5c.tar.gz yosys-84f3a796e1232b19674a412b5d011d208d923f5c.tar.bz2 yosys-84f3a796e1232b19674a412b5d011d208d923f5c.zip | |
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to '__init__.py')
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