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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-25 23:01:54 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-25 23:01:54 +0100 |
| commit | 27a918eadf11cfe6cfe0eead022c8ff3336a855e (patch) | |
| tree | 2e203f109da77bb50c88bb0cd4bcb52cc4d424ba /README | |
| parent | 331f8b8d0ba2c11aac89f15622b23a0284c538d7 (diff) | |
| parent | 3fe18c26cd020b31012e465c5a8b1db0abe64182 (diff) | |
| download | yosys-27a918eadf11cfe6cfe0eead022c8ff3336a855e.tar.gz yosys-27a918eadf11cfe6cfe0eead022c8ff3336a855e.tar.bz2 yosys-27a918eadf11cfe6cfe0eead022c8ff3336a855e.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -288,6 +288,9 @@ Verilog Attributes and non-standard features Setting the "keep" attribute on a module has the same effect as setting it on all instances of the module. +- The "keep_hierarchy" attribute on cells and modules keeps the "flatten" + command from flattening the indicated cells and modules. + - The "init" attribute on wires is set by the frontend when a register is initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis to add the necessary reset logic. |