diff options
author | Clifford Wolf <clifford@clifford.at> | 2013-03-25 17:13:14 +0100 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2013-03-25 17:13:14 +0100 |
commit | 227520f94d5fe0eb983889b61ed9b72640f1b4f4 (patch) | |
tree | ab39e242d3344e6a2b1712e99aba14f09c19d79c /README | |
parent | 37379648097cb01f6181324c69cabb677ecc06ca (diff) | |
download | yosys-227520f94d5fe0eb983889b61ed9b72640f1b4f4.tar.gz yosys-227520f94d5fe0eb983889b61ed9b72640f1b4f4.tar.bz2 yosys-227520f94d5fe0eb983889b61ed9b72640f1b4f4.zip |
Added nosync attribute and some async reset related fixes
Diffstat (limited to 'README')
-rw-r--r-- | README | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -199,6 +199,12 @@ Verilog Attributes and non-standard features prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. +- The "nosync" attribute on registers prohibits the generation of a + storage element. The register itself will always have all bits set + to 'x' (undefined). The variable may only be used as blocking assigned + temporary variable within an always block. This is mostly used internally + by yosys to synthesize verilog functions and access arrays. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset |