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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-23 08:58:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-23 08:58:34 -0700 |
| commit | f66792c43afeacdcceedde83785471e51ee12593 (patch) | |
| tree | e3fe26720e424d544375816700312e04a96a2f64 /README.md | |
| parent | c84cdc711c6f78175c3ef236c3aa7640d7485b79 (diff) | |
| download | yosys-f66792c43afeacdcceedde83785471e51ee12593.tar.gz yosys-f66792c43afeacdcceedde83785471e51ee12593.tar.bz2 yosys-f66792c43afeacdcceedde83785471e51ee12593.zip | |
Fix spelling
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -370,7 +370,7 @@ Verilog Attributes and non-standard features - When defining a macro with `define, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The - tipple double quotes are removed from the macro body. For example: + triple double quotes are removed from the macro body. For example: `define MY_MACRO(a, b) """ assign a = 23; |