diff options
author | Zachary Snow <zach@zachjs.com> | 2021-10-19 18:46:26 -0600 |
---|---|---|
committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
commit | e833c6a418103feb30f0cc3e5c482da00ee9f820 (patch) | |
tree | ef7d028ed17200f04558f3d2426f3db7ef6134cd /README.md | |
parent | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (diff) | |
download | yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.gz yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.bz2 yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.zip |
verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -489,6 +489,11 @@ Verilog Attributes and non-standard features for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this functionality. (By default these blocks are ignored.) +- The ``reprocess_after`` internal attribute is used by the Verilog frontend to + mark cells with bindings which might depend on the specified instantiated + module. Modules with such cells will be reprocessed during the ``hierarchy`` + pass once the referenced module definition(s) become available. + Non-standard or SystemVerilog features for formal verification ============================================================== |