Merge remote-tracking branch 'upstream/master'

1 files changed, 7 insertions, 1 deletions

diff --git a/README.md b/README.md
index 9bac468a7..4048ecbc7 100644
--- a/README.md
+++ b/README.md
@@ -105,12 +105,15 @@ Makefile.
 To build Yosys simply type 'make' in this directory.
 
 	$ make
-	$ make test
 	$ sudo make install
 
 Note that this also downloads, builds and installs ABC (using yosys-abc
 as executable name).
 
+Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
+
+	$ make test
+
 Getting Started
 ===============
 
@@ -312,6 +315,9 @@ Verilog Attributes and non-standard features
 - The ``dynports'' attribute is used by the Verilog front-end to mark modules
   that have ports with a width that depends on a parameter.
 
+- The ``hdlname'' attribute is used by some passes to document the original
+  (HDL) name of a module when renaming a module.
+
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
   have hidden connections that are not part of the netlist, such as IO pads.