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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:47:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 15:47:41 -0700 |
| commit | b88f0f6450a4d9db4c926a4636968f12d763096b (patch) | |
| tree | 7c70b8294cc435e40d947ccbb44d7a6c1d7bc4de /README.md | |
| parent | 2d9484c12cd1fd96eca5253c876ad545ed209f40 (diff) | |
| parent | b76fac3ac3a815568827a03b201f386b2577e010 (diff) | |
| download | yosys-b88f0f6450a4d9db4c926a4636968f12d763096b.tar.gz yosys-b88f0f6450a4d9db4c926a4636968f12d763096b.tar.bz2 yosys-b88f0f6450a4d9db4c926a4636968f12d763096b.zip | |
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -347,6 +347,12 @@ Verilog Attributes and non-standard features automatic clock buffer insertion by ``clkbufmap``. This behaviour can be overridden by providing a custom selection to ``clkbufmap``. +- The ``invertible_pin`` attribute can be set on a port to mark it as + invertible via a cell parameter. The name of the inversion parameter + is specified as the value of this attribute. The value of the inversion + parameter must be of the same width as the port, with 1 indicating + an inverted bit and 0 indicating a non-inverted bit. + - The ``iopad_external_pin`` attribute on a blackbox module's port marks it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. |