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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-05 13:51:53 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-05 13:51:53 +0200 |
| commit | 30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306 (patch) | |
| tree | 98a5d666279a6a767472b63e50edf450ed410ff7 /README.md | |
| parent | 694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f (diff) | |
| download | yosys-30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306.tar.gz yosys-30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306.tar.bz2 yosys-30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306.zip | |
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -332,6 +332,9 @@ Verilog Attributes and non-standard features that represent module parameters or localparams (when the HDL front-end is run in ``-pwires`` mode). +- Wires marked with the ``hierconn`` attribute are connected to wires with the + same name when they are imported from sub-modules by ``flatten``. + - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` from inserting another clock buffer on a net driven by such output. |