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| author | Clifford Wolf <clifford@clifford.at> | 2017-11-18 09:56:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-18 09:56:36 +0100 |
| commit | c01df04e32f7913622f40ced56fcb523ac96d35f (patch) | |
| tree | 87bb6d6a666a4246aa90bae9838b82ba62c41574 /Makefile | |
| parent | 234726c65537cf665681bf9af5bda6d57a90df23 (diff) | |
| parent | acee813a5c0d5517ea4123945e4971ddd2e5f3a4 (diff) | |
| download | yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.tar.gz yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.tar.bz2 yosys-c01df04e32f7913622f40ced56fcb523ac96d35f.zip | |
Merge pull request #453 from dh73/master
Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
Diffstat (limited to 'Makefile')
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