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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-12 11:54:20 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-12 11:54:20 +0200 |
| commit | 482d9208aa9dacb7afe21f08c882d4881581013a (patch) | |
| tree | a5a4d409f7d84cc2dc6283dcf45df3aea02cb061 /Makefile | |
| parent | 9a6cd64fc2ca46c9aed1bd03b6898c7734420c53 (diff) | |
| download | yosys-482d9208aa9dacb7afe21f08c882d4881581013a.tar.gz yosys-482d9208aa9dacb7afe21f08c882d4881581013a.tar.bz2 yosys-482d9208aa9dacb7afe21f08c882d4881581013a.zip | |
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions