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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-25 15:41:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-25 15:41:45 +0200 |
| commit | 001c9f1d45749535452d082a7c92a17954b603b8 (patch) | |
| tree | f2563fa5e64499913800699825af4b66d1573e66 /Makefile | |
| parent | 251562a4918576bd485bcdcc908c0ac780689a77 (diff) | |
| download | yosys-001c9f1d45749535452d082a7c92a17954b603b8.tar.gz yosys-001c9f1d45749535452d082a7c92a17954b603b8.tar.bz2 yosys-001c9f1d45749535452d082a7c92a17954b603b8.zip | |
Fix Verific handling of single-bit anyseq/anyconst wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions