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| author | Andrew Becker <andrew.becker@epfl.ch> | 2016-03-14 19:28:34 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-15 12:03:40 +0100 |
| commit | 81d4e9e7c1c311f837dadb1634c83b4e70929669 (patch) | |
| tree | 868cecfa8e060a8308977470ebd9e2812e7d6ce4 /CodingReadme | |
| parent | 2a8d5e64f5a994fa8f4f51c00d647ad977e42e4b (diff) | |
| download | yosys-81d4e9e7c1c311f837dadb1634c83b4e70929669.tar.gz yosys-81d4e9e7c1c311f837dadb1634c83b4e70929669.tar.bz2 yosys-81d4e9e7c1c311f837dadb1634c83b4e70929669.zip | |
Use left-recursive rule for cell_port_list in Verilog parser.
Diffstat (limited to 'CodingReadme')
0 files changed, 0 insertions, 0 deletions