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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 14:42:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:35:13 +0200 |
| commit | 397b00252dc0c4af725614bd12fc299147ba8efa (patch) | |
| tree | e7a1dfdd61f165a517036c4efdde2c53ef9076e7 /CHECKLISTS | |
| parent | 48822e79a34880c5f0b07e9889e463e7b6d7111b (diff) | |
| download | yosys-397b00252dc0c4af725614bd12fc299147ba8efa.tar.gz yosys-397b00252dc0c4af725614bd12fc299147ba8efa.tar.bz2 yosys-397b00252dc0c4af725614bd12fc299147ba8efa.zip | |
Added $shift and $shiftx cell types (needed for correct part select behavior)
Diffstat (limited to 'CHECKLISTS')
| -rw-r--r-- | CHECKLISTS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/CHECKLISTS b/CHECKLISTS index 3f824fc28..8a149a539 100644 --- a/CHECKLISTS +++ b/CHECKLISTS @@ -123,6 +123,8 @@ Things to do right away: - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells) - Add to InternalCellChecker::check() in kernel/rtlil.cc + - Add to techlibs/common/simlib.v + - Add to techlibs/common/stdcells.v Things to do after finalizing the cell interface: |