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author | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-14 12:06:57 +0200 |
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committer | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-14 12:06:57 +0200 |
commit | fe651922cbc4ab086354c04652adc986b31305fd (patch) | |
tree | e06a152dbc08ffac344c1a9139b0c43b0651239f /CHANGELOG | |
parent | 53695e6729e8ae603be7e7cd9bc8b29758d61a11 (diff) | |
parent | d4f77d408c754285969969bda3a6985c1fbe9fb6 (diff) | |
download | yosys-fe651922cbc4ab086354c04652adc986b31305fd.tar.gz yosys-fe651922cbc4ab086354c04652adc986b31305fd.tar.bz2 yosys-fe651922cbc4ab086354c04652adc986b31305fd.zip |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'CHANGELOG')
-rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |