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authorBogdan Vukobratovic <bogdan.vukobratovic@gmail.com>2019-06-14 12:06:57 +0200
committerBogdan Vukobratovic <bogdan.vukobratovic@gmail.com>2019-06-14 12:06:57 +0200
commitfe651922cbc4ab086354c04652adc986b31305fd (patch)
treee06a152dbc08ffac344c1a9139b0c43b0651239f /CHANGELOG
parent53695e6729e8ae603be7e7cd9bc8b29758d61a11 (diff)
parentd4f77d408c754285969969bda3a6985c1fbe9fb6 (diff)
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Merge remote-tracking branch 'upstream/master'
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diff --git a/CHANGELOG b/CHANGELOG
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@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
+ - Added "read_aiger" frontend
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"