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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:50:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:50:39 -0700 |
| commit | f7a9769c140f6a56e51d7384dfd8e76bf2aef66d (patch) | |
| tree | 4be49b8b30a03ac7d4deafaa7318de275d5c3a7f /CHANGELOG | |
| parent | ac2aff9e28a087a9a2697cd6ccf754af738903a7 (diff) | |
| parent | a91ea6612a73568782c80bd12ce2875353e2b5c5 (diff) | |
| download | yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.tar.gz yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.tar.bz2 yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |