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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:35:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:35:06 -0700 |
| commit | f4fd41d5d2e15868540c2a09e23dbc90bf15e567 (patch) | |
| tree | eaf72ecc07ab9920770e33d02bb85f6356a441b3 /CHANGELOG | |
| parent | 78b7d8f531cfec661931c08547d90b3f08ae65b3 (diff) | |
| parent | 55bf8f69e085caa0a3f0ccae8bf231f77aba6bbc (diff) | |
| download | yosys-f4fd41d5d2e15868540c2a09e23dbc90bf15e567.tar.gz yosys-f4fd41d5d2e15868540c2a09e23dbc90bf15e567.tar.bz2 yosys-f4fd41d5d2e15868540c2a09e23dbc90bf15e567.zip | |
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -27,6 +27,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "opt_share" pass, run as part of "opt -full" - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping - Removed "ice40_unlut" + - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" |