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| author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2019-04-30 13:22:33 +0200 |
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| committer | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2019-04-30 13:22:33 +0200 |
| commit | dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4 (patch) | |
| tree | 8d6a4b7ebcf96a2fe5b5bdb21b821555a3a3b994 /CHANGELOG | |
| parent | 124a284487ce4c7b58f2377f04123e15e83e478d (diff) | |
| parent | 314ff1e4ca00ef8024bbb0d2f031efd78b01f9a1 (diff) | |
| download | yosys-dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4.tar.gz yosys-dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4.tar.bz2 yosys-dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" Yosys 0.7 .. Yosys 0.8 |