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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:07:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 20:07:31 -0700 |
| commit | dbb8c8caaa50d83c12665b7cfd11d79e8af06196 (patch) | |
| tree | 4422b6cb7f3c8560847ead3545ea98b3638404eb /CHANGELOG | |
| parent | b9ff0503f39795a1f749c955b129d9972fe03f0a (diff) | |
| parent | c226af3f56957cc69b2ce8bb68a8259e26121ddc (diff) | |
| download | yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.tar.gz yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.tar.bz2 yosys-dbb8c8caaa50d83c12665b7cfd11d79e8af06196.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -22,6 +22,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -dmux=<cost>" - Added "muxcover -nopartial" - Added "muxpack" pass + - Added "write_xaiger" backend - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) |