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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 16:54:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 16:54:12 -0700 |
| commit | c04482b07798cfcca3218cfafe0998eeb6a88f76 (patch) | |
| tree | 7ab5afff2db3c70121833a88f5deeb6b3ce41479 /CHANGELOG | |
| parent | 2c40b667850578eb7bb2dceb3a9beda0fdbfe7e7 (diff) | |
| download | yosys-c04482b07798cfcca3218cfafe0998eeb6a88f76.tar.gz yosys-c04482b07798cfcca3218cfafe0998eeb6a88f76.tar.bz2 yosys-c04482b07798cfcca3218cfafe0998eeb6a88f76.zip | |
Update CHANGELOG
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "rename -src" - Added "equiv_opt" pass - Added "read_aiger" frontend + - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9) - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" |