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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-17 16:29:25 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-17 16:29:25 +0100 |
| commit | 97b49d6e4532e7bfd183c8d87113e4993b246b77 (patch) | |
| tree | 9bb39af9bf93f7ce38ef9f4bb351732f8ca9a410 /CHANGELOG | |
| parent | ce701fd3348f43e66a445ef58e4818adaf3e574d (diff) | |
| parent | 4effb38e6d318e2e233bdfa9f2e0bb67e4998bf0 (diff) | |
| download | yosys-97b49d6e4532e7bfd183c8d87113e4993b246b77.tar.gz yosys-97b49d6e4532e7bfd183c8d87113e4993b246b77.tar.bz2 yosys-97b49d6e4532e7bfd183c8d87113e4993b246b77.zip | |
Merge pull request #741 from whitequark/ilang_slice_sigspec
read_ilang: allow slicing all sigspecs, not just wires
Diffstat (limited to 'CHANGELOG')
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