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authorZachary Snow <zach@zachjs.com>2022-01-11 23:51:08 -0700
committerZachary Snow <zachary.j.snow@gmail.com>2022-02-11 21:01:51 +0100
commit90bb47d18140e381e65bd2b51fd793a0692b56a0 (patch)
treea9dd99b1a9a28640fd2777d5fb38aa89bd2a30d2 /CHANGELOG
parentca876e7c12856ed52e2a30e3ebbc7836ae18dfb9 (diff)
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verilog: fix const func eval with upto variables
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diff --git a/CHANGELOG b/CHANGELOG
index 1451ea07c..4312ec7ee 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -5,6 +5,10 @@ List of major changes and improvements between releases
Yosys 0.14 .. Yosys 0.14-dev
--------------------------
+ * Verilog
+ - Fixed evaluation of constant functions with variables or arguments with
+ reversed dimensions
+
Yosys 0.13 .. Yosys 0.14
--------------------------