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authorEddie Hung <eddie@fpgeh.com>2019-09-29 11:26:22 -0700
committerGitHub <noreply@github.com>2019-09-29 11:26:22 -0700
commit8474c5b366660153cae03a9de4af8e1ed809856d (patch)
treecd157ab16b528565ced19f422ffece1c6110f53e /CHANGELOG
parentce0631c371f69f0132ea9ee4bc8f5ee576dbb1a3 (diff)
parentb3d8a60cbd94176076f23c4ea6c94ec24e6773e0 (diff)
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Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Diffstat (limited to 'CHANGELOG')
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diff --git a/CHANGELOG b/CHANGELOG
index 0adf1e813..481f33a6c 100644
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+++ b/CHANGELOG
@@ -43,6 +43,12 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "-match-init" option to "dff2dffs" pass
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
+ - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+ - Added "ice40_dsp" for Lattice iCE40 DSP packing
+ - Added "xilinx_dsp" for Xilinx DSP packing
+ - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
+ - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
+ - "synth_ice40 -dsp" to infer DSP blocks
Yosys 0.8 .. Yosys 0.9
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