aboutsummaryrefslogtreecommitdiffstats
path: root/CHANGELOG
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2019-11-22 15:32:29 +0100
committerGitHub <noreply@github.com>2019-11-22 15:32:29 +0100
commit72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d (patch)
treeb499121c6a6f5bd269c871ba08d52656784e03c9 /CHANGELOG
parente110df9c484d5c87429c55da1c1d83fd509a78b3 (diff)
parentb60f32c6ecc27e0fa1f81a1055cfd1105ed647bd (diff)
downloadyosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.tar.gz
yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.tar.bz2
yosys-72d2ef6fd071a8b2b9e1a77ddab3a9d632aa0f3d.zip
Merge pull request #1511 from YosysHQ/dave/always
sv: Error checking for always_comb, always_latch and always_ff
Diffstat (limited to 'CHANGELOG')
-rw-r--r--CHANGELOG2
1 files changed, 2 insertions, 0 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 1fc139d49..a49c27b05 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -51,6 +51,8 @@ Yosys 0.9 .. Yosys 0.9-dev
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
- Added "check -mapped"
+ - Added checking of SystemVerilog always block types (always_comb,
+ always_latch and always_ff)
Yosys 0.8 .. Yosys 0.9
----------------------