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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:44:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 17:44:21 -0700 |
| commit | 6c2cb519965ac9b4057a90cd46f474c092967be2 (patch) | |
| tree | 45f545af7700a244f64a0e42f96fae37df9f2914 /CHANGELOG | |
| parent | 301e065aeee2d6a4b5009ebdc50028bafd3aac5d (diff) | |
| parent | 1abe93e48d8bb78cd0753d46dfbe1885a1e803eb (diff) | |
| download | yosys-6c2cb519965ac9b4057a90cd46f474c092967be2.tar.gz yosys-6c2cb519965ac9b4057a90cd46f474c092967be2.tar.bz2 yosys-6c2cb519965ac9b4057a90cd46f474c092967be2.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 5 |
1 files changed, 3 insertions, 2 deletions
@@ -16,16 +16,17 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "shregmap -tech xilinx" - Added "read_aiger" frontend - Added "shregmap -tech xilinx" - - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) + - Added "muxpack" pass - Extended "muxcover -mux{4,8,16}=<cost>" - Fixed sign extension of unsized constants with 'bx and 'bz MSB - - Added "muxpack" pass + - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - "synth_xilinx" to now infer wide multiplexers (-nomux to disable) |