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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:00:50 -0700 |
| commit | 6872805a3eb738a0a5921b232022abfd507cebb8 (patch) | |
| tree | b871344e8f96cd30c5a6bc3f275476e30f792de0 /CHANGELOG | |
| parent | 6b51c154c6812f58676402ebbbdbb18d053ca4be (diff) | |
| parent | bb2d5bc4f85ac95104fbd2591ad92ebf0c22e11d (diff) | |
| download | yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.gz yosys-6872805a3eb738a0a5921b232022abfd507cebb8.tar.bz2 yosys-6872805a3eb738a0a5921b232022abfd507cebb8.zip | |
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -14,6 +14,10 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth -abc9" (experimental) - Added "script -scriptwire - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable) + - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels in synth_intel (e.g. bram -> map_bram) + - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram) - Added automatic gzip decompression for frontends - Added $_NMUX_ cell type - Added automatic gzip compression (based on filename extension) for backends @@ -24,6 +28,10 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -ise" (experimental) - Added "synth_xilinx -iopad" - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable) + - Improvements in pmgen: subpattern and recursive matches + - Added "opt_share" pass, run as part of "opt -full" + - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping + - Removed "ice40_unlut" Yosys 0.8 .. Yosys 0.8-dev -------------------------- |