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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 12:45:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 12:45:40 -0700 |
| commit | 3b8f3a93ada563fbae62772b0bf642bb54170954 (patch) | |
| tree | 5744645c4b5394ace5e9c88c2a500a8b7694104a /CHANGELOG | |
| parent | d0bbf9e4d4a508179b55a0cc7793d984f3318f7c (diff) | |
| download | yosys-3b8f3a93ada563fbae62772b0bf642bb54170954.tar.gz yosys-3b8f3a93ada563fbae62772b0bf642bb54170954.tar.bz2 yosys-3b8f3a93ada563fbae62772b0bf642bb54170954.zip | |
Add CHANGELOG entry
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -19,6 +19,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "read_aiger" frontend - Extended "muxcover -mux{4,8,16}=<cost>" - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - Fixed sign extension of unsized constants with 'bx and 'bz MSB Yosys 0.7 .. Yosys 0.8 @@ -32,7 +33,7 @@ Yosys 0.7 .. Yosys 0.8 - Added "write_verilog -decimal" - Added "scc -set_attr" - Added "verilog_defines" command - - Remeber defines from one read_verilog to next + - Remember defines from one read_verilog to next - Added support for hierarchical defparam - Added FIRRTL back-end - Improved ABC default scripts |