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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:03:18 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-06 09:03:18 -0800 |
| commit | ffd38cb5ea7a6b7d93a49c90bf603131f6c760af (patch) | |
| tree | 854cb703bc7f2f70ba1e4029516e89f057d57354 | |
| parent | e62eb02c1dd3074e58c9be64b8bb3b13b8d9a1ea (diff) | |
| download | yosys-ffd38cb5ea7a6b7d93a49c90bf603131f6c760af.tar.gz yosys-ffd38cb5ea7a6b7d93a49c90bf603131f6c760af.tar.bz2 yosys-ffd38cb5ea7a6b7d93a49c90bf603131f6c760af.zip | |
Reword (* abc9_flop *) description
| -rw-r--r-- | README.md | 5 |
1 files changed, 3 insertions, 2 deletions
@@ -376,10 +376,11 @@ Verilog Attributes and non-standard features - The port attribute ``abc9_arrival`` specifies an integer (for output ports only) to be used as the arrival time of this sequential port. It can be used, for example, to specify the clk-to-Q delay of a flip-flop for consideration - during techmapping. + during `abc9` techmapping. - The module attribute ``abc9_flop`` is a boolean marking the module as a - whitebox that describes the synchronous behaviour of a flip-flop. + flip-flop. This allows `abc9` to analyse its contents in order to perform + sequential synthesis. - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks |