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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-09-23 16:22:46 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-23 16:22:46 +0200 |
| commit | fcd1be14225730147941aa78a85d0c30ccf1cf30 (patch) | |
| tree | 7d905cc2d823493c13c7b06a7429c87cbfab4451 | |
| parent | 0ab726e204820f674ea7d4024beee3bca29a89b7 (diff) | |
| parent | c4c68e8d860664d2b5c62f31f46ce1a24e222b86 (diff) | |
| download | yosys-fcd1be14225730147941aa78a85d0c30ccf1cf30.tar.gz yosys-fcd1be14225730147941aa78a85d0c30ccf1cf30.tar.bz2 yosys-fcd1be14225730147941aa78a85d0c30ccf1cf30.zip | |
Merge pull request #3486 from daglem/fix-flowmap-crash
Fix crash in flowmap
| -rw-r--r-- | passes/techmap/flowmap.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index dfdbe6b88..579503a0b 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1406,7 +1406,8 @@ struct FlowmapWorker RTLIL::SigSpec lut_a, lut_y = node; for (auto input_node : input_nodes) lut_a.append(input_node); - lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); + if ((int)input_nodes.size() < minlut) + lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); mapped_nodes.insert(node); |