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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-02 13:19:04 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-02 13:19:04 +0100 |
| commit | f912e029de64b17316c2d285bf728151e6bd6de3 (patch) | |
| tree | 0616e8699a7d83cef19855bb1163ec5294f34999 | |
| parent | 943329c1dc25609f848d4f5ce837c362e5fd2642 (diff) | |
| download | yosys-f912e029de64b17316c2d285bf728151e6bd6de3.tar.gz yosys-f912e029de64b17316c2d285bf728151e6bd6de3.tar.bz2 yosys-f912e029de64b17316c2d285bf728151e6bd6de3.zip | |
Added roadmap to readme file
| -rw-r--r-- | README | 9 |
1 files changed, 9 insertions, 0 deletions
@@ -280,6 +280,15 @@ and after each occurrence of PRIi64 in the header file: sudo sed -i 's/PRIi64/ & /' /usr/include/minisat/utils/Options.h +Roadmap / Large-scale TODOs +=========================== + +- Technology mapping for real-world applications (specific FPGAs and ASIC processes) +- Improve standard complience of const folding and parameters (mostly expression widths) +- Implement SAT-based formal equivialence checker based on existing SAT framework +- Re-implement Verilog frontend (cleaner AST format, pipeline of well structured AST transformations) + + TODOs / Open Bugs ================= |