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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-06 18:45:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-06 18:45:31 +0100 |
| commit | f839b842a23a657c2431c84ff5a54b7684025622 (patch) | |
| tree | df2b3e0b751093dea373050a881630cb488cb459 | |
| parent | 204572d926921608b8d1c3d59e96c7f25051527d (diff) | |
| download | yosys-f839b842a23a657c2431c84ff5a54b7684025622.tar.gz yosys-f839b842a23a657c2431c84ff5a54b7684025622.tar.bz2 yosys-f839b842a23a657c2431c84ff5a54b7684025622.zip | |
Fixed handling of undef values in POS cells in ConstEval
| -rw-r--r-- | kernel/calc.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/kernel/calc.cc b/kernel/calc.cc index efb09c398..f2cbd6f42 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -418,9 +418,7 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo RTLIL::Const arg1_ext = arg1; while (int(arg1_ext.bits.size()) < result_len) arg1_ext.bits.push_back(signed1 && arg1_ext.bits.size() ? arg1_ext.bits.back() : RTLIL::State::S0); - - RTLIL::Const zero(RTLIL::State::S0, 1); - return RTLIL::const_add(zero, arg1_ext, false, signed1, result_len); + return arg1_ext; } RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) |