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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-18 09:33:34 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-18 09:33:34 +0200 |
| commit | f564a658517f510dce12c5ef8bcc2a9ec9dd055b (patch) | |
| tree | 03574547329d666ad0e229fa2529fd254a083273 | |
| parent | f78fa718be5ff611547dbadce5f2dc3e9fb59384 (diff) | |
| download | yosys-f564a658517f510dce12c5ef8bcc2a9ec9dd055b.tar.gz yosys-f564a658517f510dce12c5ef8bcc2a9ec9dd055b.tar.bz2 yosys-f564a658517f510dce12c5ef8bcc2a9ec9dd055b.zip | |
Added ice40 test_arith
| -rw-r--r-- | techlibs/ice40/tests/test_arith.v | 3 | ||||
| -rw-r--r-- | techlibs/ice40/tests/test_arith.ys | 10 |
2 files changed, 13 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_arith.v b/techlibs/ice40/tests/test_arith.v new file mode 100644 index 000000000..77f79b973 --- /dev/null +++ b/techlibs/ice40/tests/test_arith.v @@ -0,0 +1,3 @@ +module test(input [4:0] a, b, c, output [4:0] y); + assign y = ((a+b) ^ (a-c)) - ((a*b) + (a*c) - (b*c)); +endmodule diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys new file mode 100644 index 000000000..160c767fb --- /dev/null +++ b/techlibs/ice40/tests/test_arith.ys @@ -0,0 +1,10 @@ +read_verilog test_arith.v +synth_ice40 +techmap -map ../cells_sim.v +rename test gate + +read_verilog test_arith.v +rename test gold + +miter -equiv -flatten -make_outputs gold gate miter +sat -verify -prove trigger 0 -show-ports miter |