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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:21:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:21:57 -0700 |
| commit | efdb057c6ad5ba0fe05a597ba5f080067f061aad (patch) | |
| tree | 4ebb5b202adb9a7885bd208340773e4231e223f1 | |
| parent | cdbcd2efbdc7980aaad95744464c17553d782cd0 (diff) | |
| download | yosys-efdb057c6ad5ba0fe05a597ba5f080067f061aad.tar.gz yosys-efdb057c6ad5ba0fe05a597ba5f080067f061aad.tar.bz2 yosys-efdb057c6ad5ba0fe05a597ba5f080067f061aad.zip | |
write_xaiger to skip POs driven by 1'bx
| -rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 1485e2b0c..12b23cfe9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -152,9 +152,13 @@ struct XAigerWriter } if (wire->port_output || keep) { - if (bit != wirebit) - alias_map[wirebit] = bit; - output_bits.insert(wirebit); + if (bit != RTLIL::Sx) { + if (bit != wirebit) + alias_map[wirebit] = bit; + output_bits.insert(wirebit); + } + else + log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); } } } |