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| author | Clifford Wolf <clifford@clifford.at> | 2018-03-27 14:12:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-27 14:12:57 +0200 |
| commit | ee3c12d6d9cbdb213c3c203d563c040867c70770 (patch) | |
| tree | 2dd02cc0315da89b4fe638790e1c14768ef7fbf2 | |
| parent | c652774ca26416c4afeb4894b315814e20c42551 (diff) | |
| download | yosys-ee3c12d6d9cbdb213c3c203d563c040867c70770.tar.gz yosys-ee3c12d6d9cbdb213c3c203d563c040867c70770.tar.bz2 yosys-ee3c12d6d9cbdb213c3c203d563c040867c70770.zip | |
Chenged "extensions_map" to "extensions_list" in hierarchy.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 21a232572..ba960faf4 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -173,14 +173,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &dir : libdirs) { - static const std::map<std::string, std::string> extensions_map = + static const vector<pair<string, string>> extensions_list = { {".v", "verilog"}, {".sv", "verilog -sv"}, {".il", "ilang"} }; - for (auto &ext : extensions_map) + for (auto &ext : extensions_list) { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first; if (check_file_exists(filename)) { |