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| author | Clifford Wolf <clifford@clifford.at> | 2018-09-23 10:32:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-09-23 10:32:54 +0200 |
| commit | eb452ffb2861ceac572a4bef6dddb8db3b79deb7 (patch) | |
| tree | f7d7c63ef13ce3d9af9a87fdd86f3e95ffa89c19 | |
| parent | 9659f7a99effda1bb699f3843d3819f248c05bd0 (diff) | |
| download | yosys-eb452ffb2861ceac572a4bef6dddb8db3b79deb7.tar.gz yosys-eb452ffb2861ceac572a4bef6dddb8db3b79deb7.tar.bz2 yosys-eb452ffb2861ceac572a4bef6dddb8db3b79deb7.zip | |
Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 2389d7d31..63cf646e9 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -881,9 +881,15 @@ param_decl_list: single_param_decl: TOK_ID '=' expr { - if (astbuf1 == nullptr) - frontend_verilog_yyerror("syntax error"); - AstNode *node = astbuf1->clone(); + AstNode *node; + if (astbuf1 == nullptr) { + if (!sv_mode) + frontend_verilog_yyerror("syntax error"); + node = new AstNode(AST_PARAMETER); + node->children.push_back(AstNode::mkconst_int(0, true)); + } else { + node = astbuf1->clone(); + } node->str = *$1; delete node->children[0]; node->children[0] = $3; |