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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 17:48:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 18:01:41 -0700 |
| commit | e730a595eeee1d9936a892c2477c99593d64bcfe (patch) | |
| tree | 86f15061b80b40dac97c875539faea4da473e2cb | |
| parent | 62c66406ad69c4cf02c3edc843d80e0e2b05c384 (diff) | |
| download | yosys-e730a595eeee1d9936a892c2477c99593d64bcfe.tar.gz yosys-e730a595eeee1d9936a892c2477c99593d64bcfe.tar.bz2 yosys-e730a595eeee1d9936a892c2477c99593d64bcfe.zip | |
Add test
| -rw-r--r-- | tests/various/peepopt.ys | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 6bca62e2b..dc0acf3ca 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -173,3 +173,34 @@ select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 2 t:$mux select -assert-count 2 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + initial o <= 4'b0010; + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +#equiv_opt -assert peepopt + +design -save gold +peepopt +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 1 -verify -prove-asserts -show-ports miter + +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D |