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| author | Kaj Tuomi <kaj.tuomi@siru.fi> | 2016-09-08 10:57:16 +0300 |
|---|---|---|
| committer | Kaj Tuomi <kaj.tuomi@siru.fi> | 2016-09-08 10:57:16 +0300 |
| commit | df4ab169a7ae84f9380e658e3ac5958a3d3e57d3 (patch) | |
| tree | 3f12c8e961e70949ca16b93aa53bda6eec81ed36 | |
| parent | 209a3d9ffcb5f7efbe60b0e0d45755329532535e (diff) | |
| download | yosys-df4ab169a7ae84f9380e658e3ac5958a3d3e57d3.tar.gz yosys-df4ab169a7ae84f9380e658e3ac5958a3d3e57d3.tar.bz2 yosys-df4ab169a7ae84f9380e658e3ac5958a3d3e57d3.zip | |
Typo fix.
| -rw-r--r-- | passes/memory/memory_share.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index bcb7433a2..ca09ac52c 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -753,7 +753,7 @@ struct MemorySharePass : public Pass { log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); + log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) MemoryShareWorker(design, module); |