Bugfix in memory_dff

2 files changed, 27 insertions, 1 deletions

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 3373369f6..2eec0207b 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -32,6 +32,7 @@ struct MemoryDffWorker
 	dict<SigBit, SigBit> invbits;
 	dict<SigBit, int> sigbit_users_count;
 	dict<SigSpec, Cell*> mux_cells_a, mux_cells_b;
+	pool<Cell*> forward_merged_dffs, candidate_dffs;
 
 	MemoryDffWorker(Module *module) : module(module), sigmap(module) { }
 
@@ -46,6 +47,9 @@ struct MemoryDffWorker
 
 			for (auto cell : dff_cells)
 			{
+				if (after && forward_merged_dffs.count(cell))
+					continue;
+
 				SigSpec this_clk = cell->getPort("\\CLK");
 				bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 
@@ -71,6 +75,7 @@ struct MemoryDffWorker
 				bit = d;
 				clk = this_clk;
 				clk_polarity = this_clk_polarity;
+				candidate_dffs.insert(cell);
 				goto replaced_this_bit;
 			}
 
@@ -87,6 +92,7 @@ struct MemoryDffWorker
 
 		RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
 		bool clk_polarity = 0;
+		candidate_dffs.clear();
 
 		RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
 		if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
@@ -106,13 +112,18 @@ struct MemoryDffWorker
 			return;
 		}
 
-		if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
+		if (clk != RTLIL::SigSpec(RTLIL::State::Sx))
+		{
+			for (auto cell : candidate_dffs)
+				forward_merged_dffs.insert(cell);
+
 			cell->setPort("\\CLK", clk);
 			cell->setPort("\\ADDR", sig_addr);
 			cell->setPort("\\DATA", sig_data);
 			cell->setPort("\\EN", sig_en);
 			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+
 			log("merged $dff to cell.\n");
 			return;
 		}
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index 67f89cd75..d58ed9d1a 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -228,3 +228,18 @@ module memtest09 (
     end
 endmodule
 
+// ----------------------------------------------------------
+
+module memtest10(input clk, input [5:0] din, output [5:0] dout);
+        reg [5:0] queue [0:3];
+        integer i;
+
+        always @(posedge clk) begin
+                queue[0] <= din;
+                for (i = 1; i < 4; i=i+1) begin
+                        queue[i] <= queue[i-1];
+                end
+        end
+
+	assign dout = queue[3];
+endmodule