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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-29 10:00:01 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-29 12:41:43 +0200 |
| commit | dc18bf1969e3550a629ffa4722ad40758fc32535 (patch) | |
| tree | 52f7991cd916997c925543a83736951390b80f64 | |
| parent | 773b056ffbdf8ab2ee78febd2d3029a61e526f55 (diff) | |
| download | yosys-dc18bf1969e3550a629ffa4722ad40758fc32535.tar.gz yosys-dc18bf1969e3550a629ffa4722ad40758fc32535.tar.bz2 yosys-dc18bf1969e3550a629ffa4722ad40758fc32535.zip | |
opt_expr: Fix handling of $_XNOR_ cells with A = B.
Fixes #2311.
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 | ||||
| -rw-r--r-- | tests/opt/bug2311.ys | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 649ad83a6..8aae1a731 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -604,7 +604,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.const_xnor"); // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ - int width = cell->getParam(ID::Y_WIDTH).as_int(); + int width = GetSize(cell->getPort(ID::Y)); replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width)); goto next_cell; } diff --git a/tests/opt/bug2311.ys b/tests/opt/bug2311.ys new file mode 100644 index 000000000..455147cd3 --- /dev/null +++ b/tests/opt/bug2311.ys @@ -0,0 +1,14 @@ +read_verilog -icells << EOT + +module top(...); + +input A; +output Y; + +$_XNOR_ x (.A(A), .B(A), .Y(Y)); + +endmodule + +EOT + +equiv_opt -assert opt_expr |