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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-25 10:33:18 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-25 10:33:18 +0200 |
| commit | d086224a39fcd488062d7f75cc936cce5435069c (patch) | |
| tree | a63703d5fabc07ec6db777d56bb388b2ac3c99a7 | |
| parent | b1d6f05fa2156017f50383d01d49342c8ec5e209 (diff) | |
| parent | d57c85111f4136e5ae098aa42cd337f82dd4b57e (diff) | |
| download | yosys-d086224a39fcd488062d7f75cc936cce5435069c.tar.gz yosys-d086224a39fcd488062d7f75cc936cce5435069c.tar.bz2 yosys-d086224a39fcd488062d7f75cc936cce5435069c.zip | |
Merge pull request #150 from azonenberg/master
GreenPak analog comparator support
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 706e955b6..1152ffe63 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -13,6 +13,19 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT); assign OUT = INIT[{IN3, IN2, IN1, IN0}]; endmodule +module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT); + + parameter BANDWIDTH = "HIGH"; + parameter VIN_ATTEN = 1; + parameter VIN_ISRC_EN = 0; + parameter HYSTERESIS = 0; + + initial OUT = 0; + + //cannot simulate mixed signal IP + +endmodule + module GP_BANDGAP(output reg OK, output reg VOUT); parameter AUTO_PWRDN = 1; parameter CHOPPER_EN = 1; |