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| author | Jannis Harder <me@jix.one> | 2022-05-24 14:32:14 +0200 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-05-24 23:03:31 -0400 |
| commit | cffec1f95f0ac4bad1deb24bf7f921bd93145a16 (patch) | |
| tree | c66eeb0e812b0519e8f72791c70e2b6dc44d7df3 | |
| parent | c525b5f91925bd51194ead99a4ecace313f9945c (diff) | |
| download | yosys-cffec1f95f0ac4bad1deb24bf7f921bd93145a16.tar.gz yosys-cffec1f95f0ac4bad1deb24bf7f921bd93145a16.tar.bz2 yosys-cffec1f95f0ac4bad1deb24bf7f921bd93145a16.zip | |
verilog: fix signedness when removing unreachable cases
| -rw-r--r-- | CHANGELOG | 5 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 1 | ||||
| -rw-r--r-- | tests/verilog/unreachable_case_sign.ys | 33 |
3 files changed, 39 insertions, 0 deletions
@@ -5,6 +5,11 @@ List of major changes and improvements between releases Yosys 0.17 .. Yosys 0.17-dev -------------------------- + * Verilog + - Fixed an issue where simplifying case statements by removing unreachable + cases could result in the wrong signedness being used for comparison with + the remaining cases + Yosys 0.16 .. Yosys 0.17 -------------------------- * New commands and options diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bd3e09c4b..4d7c4f522 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1531,6 +1531,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, detectSignWidth(width_hint, sign_hint); while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { + children[0]->is_signed = sign_hint; RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint); std::vector<AstNode*> new_children; new_children.push_back(children[0]); diff --git a/tests/verilog/unreachable_case_sign.ys b/tests/verilog/unreachable_case_sign.ys new file mode 100644 index 000000000..25bc0c6f0 --- /dev/null +++ b/tests/verilog/unreachable_case_sign.ys @@ -0,0 +1,33 @@ +logger -expect-no-warnings + +read_verilog -formal <<EOT +module top(input clk); + reg good = 0; + + always @(posedge clk) begin + case (4'sb1111) 15: good = 1; 4'b0000: ; endcase + assert (good); + end +endmodule +EOT + +prep -top top +sim -n 3 -clock clk + +design -reset + +read_verilog -formal <<EOT +module top(input clk); + reg good = 1; + reg signed [1:0] case_value = -1; + + always @(posedge clk) begin + case (4'sb1111) 4'b0000: ; case_value: good = 0; endcase + assert (good); + end +endmodule +EOT + +prep -top top +sim -n 3 -clock clk + |