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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:03:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:03:11 +0200 |
| commit | cf1ba46fa029468869fb3af468d18ad72c8a9c4a (patch) | |
| tree | b753e86cc0b82360d738aa013fad7f4813cabd20 | |
| parent | cbd9b8a3f38b15874d36e5ba116536a981756411 (diff) | |
| download | yosys-cf1ba46fa029468869fb3af468d18ad72c8a9c4a.tar.gz yosys-cf1ba46fa029468869fb3af468d18ad72c8a9c4a.tar.bz2 yosys-cf1ba46fa029468869fb3af468d18ad72c8a9c4a.zip | |
Re-added clean after techmap in synth_xilinx
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index da6c0a4b2..d66722195 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -124,6 +124,7 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); + log(" clean\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); @@ -280,6 +281,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + Pass::call(design, "clean"); } if (check_label(active, run_from, run_to, "check")) |