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| author | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 18:01:44 +0200 |
|---|---|---|
| committer | Stefan Biereigel <stefan@biereigel.de> | 2019-05-27 18:01:44 +0200 |
| commit | cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485 (patch) | |
| tree | 9037dd10ddc8329a7e8b7fdfd7228a2d46d5ac23 | |
| parent | ed625a3102233bf9c9af17e56575dc4a0ed8946c (diff) | |
| download | yosys-cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485.tar.gz yosys-cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485.tar.bz2 yosys-cd12f2ddcfbdbfbf147afc2c90ddc54ec1f74485.zip | |
remove leftovers from ast data structures
| -rw-r--r-- | frontends/ast/ast.cc | 3 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 1 |
2 files changed, 0 insertions, 4 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 963152588..44b8863f9 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -51,7 +51,6 @@ namespace AST_INTERNAL { std::map<std::string, AstNode*> current_scope; const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; - std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map; AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; bool current_always_clocked; @@ -943,8 +942,6 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } - wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>(); - if (!defer) { bool blackbox_module = flag_lib; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index c2a7744c4..6c19dc7e6 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -327,7 +327,6 @@ namespace AST_INTERNAL extern std::map<std::string, AST::AstNode*> current_scope; extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; - extern std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map; extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; extern bool current_always_clocked; |